The energy consumption of an electronic device, such as a digital processor, is a critical issue in many cases. For example, technologies such as the Internet-of-Things “IoT”, the Industrial Internet “II”, and the Internet-of-Everything “IoE” are on the threshold of a massive breakthrough, and the major drivers behind the breakthrough are ubiquitous wireless processing nodes. However, the energy consumption of transmitting a bit across a given distance does not scale with Moore's law as advantageously as the digital processing within a wireless node. Therefore, the energy cost of wireless transmission will proportionally grow when compared to digital processing. Increasing the energy efficiency thus requires increasing the amount of intra-node processing in order to minimize the wireless transmission of data. Therefore, the processor and the digital signal processing “DSP” will become one of the, if not the, most important parts to be optimized. This will be compounded by the increasing functionalities of the wireless node, such as e.g. Machine Learning, Video, etc.
Increasing the energy efficiency may result in a design where different sections of an electronic device operate with different supply voltages. For example, in ultra-low-power processor scenarios, memory blocks may require supply voltages that are higher than supply voltages of processors. Thus, the memory blocks belong to a higher voltage domain of the electronic device whereas the processors belong to a lower voltage domain of the electronic device. In some cases and especially in conjunction with central processing units “CPU”, a supply voltage of a processor is often called core voltage.
One or more level shifters is/are typically required in order to transfer digital data from a lower voltage domain operating at a lower voltage to a higher voltage domain operating at a higher voltage. The energy consumption of the level shifters needs to be minimized and is especially important for example in cases where wide data buses are under the need for level shifting.
A known approach to reduce energy consumption of a level shifter is to use pre-charging where the level shifter is pre-charged to the voltage of a higher voltage domain prior to transferring digital data from a lower voltage domain to the higher voltage domain. The pre-charging is typically called a pre-charging phase and the transfer of the digital data is typically called an evaluation phase. Level shifters where the pre-charging is used are presented e.g. in publications U.S. Pat. No. 8,860,488 and US20150207506. In the level shifters described in U.S. Pat. No. 8,860,488 and US20150207506, two cross coupled p-channel metal oxide semiconductor “PMOS” transistors are utilized and thus two separate discharging branches are needed. Publication WO2011097628 describes a level shifter where only one pre-charged branch and only one discharging path are needed and where the pre-charged output terminal of the level shifter is kept at a high logical value with the aid of a keeper circuit. The keeper circuit, however, needs gating information from another level shifter with a delay, and this arrangement increases the energy consumption as well as the layout area.